LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY core_32_tb IS
END core_32_tb;



ARCHITECTURE bhv OF core_32_tb IS
  
  signal clk		           : STD_LOGIC := '1';	
	signal inst_ram_input  : std_logic_vector(35 downto 0) := (others => '0');
	signal inst_ram_addr   : unsigned(6 downto 0) := (others => '0');
	signal inst_ram_wren   : std_logic	:= '0';
	
	signal data_ram_input  : std_logic_vector(35 downto 0) := (others => '0');
	signal data_ram_addr   : unsigned(6 downto 0) := (others => '0');
  signal data_ram_wren   : std_logic := '0';
		
	signal reg_out 		      : std_logic_vector(31 downto 0);
	
	signal clk_counter : unsigned(31 downto 0) := (others => '0'); 

   component core_32 IS
   PORT
   (
      clk		           : IN STD_LOGIC;
		
		  inst_ram_input  : in std_logic_vector(35 downto 0);
		  inst_ram_addr   : in unsigned(6 downto 0);
		  inst_ram_wren   : in std_logic;
		
		  data_ram_input  : in std_logic_vector(35 downto 0);
		  data_ram_addr   : in unsigned(6 downto 0);
		  data_ram_wren   : in std_logic;
		
		  reg_out 		      : out std_logic_vector(31 downto 0)
   );
   END component;

BEGIN
	
	
	dut : core_32 
   PORT map
   (
      clk		           => clk,
	    inst_ram_input  => inst_ram_input,
	    inst_ram_addr   => inst_ram_addr,
	    inst_ram_wren   => inst_ram_wren,
	    data_ram_input  => data_ram_input,
		  data_ram_addr   => data_ram_addr,
		  data_ram_wren   => data_ram_wren,
		  reg_out 		      => reg_out
   );
	
	clk <= not clk after 5 ns;
	
	
	process begin
	 wait for 50 ns;
	 inst_ram_wren <= '1';
	 inst_ram_input <= x"0410000aa";    -- 3c3c in reg0
	 wait for 10 ns;
	 inst_ram_input <= x"020040001";    -- load memaddr 1 in reg4
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"041010055";    -- 3c3c in reg1
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"043050101";    -- set zeroflag
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"042050504";    -- 5 = 5 + 4
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"042020001";    -- reg2 = reg0 + reg1
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"04B030001";    -- reg3 = reg0 * reg1
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"041040001";    -- reg4 = 1
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"042070505";    -- reg4 = 1
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"080000004";    -- jump 3
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"04106abcd";    -- reg6 = abcd
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"000000000";    -- nop
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_input <= x"04206abcd";    -- reg6 = abcd
	 inst_ram_addr <= inst_ram_addr +1;
	 wait for 10 ns;
	 inst_ram_wren <= '0';
	 wait;  
	end process;
	
	
	process begin
	 wait for 50 ns;
	 data_ram_wren <= '1';
	 data_ram_input <= x"000000001";
	 data_ram_addr <=  "0000001";    -- 
	 wait for 10 ns;
   data_ram_wren <= '1';
	 data_ram_input <= x"000000004";
	 data_ram_addr <=  "0000010";    --
	 wait for 10 ns;
	 data_ram_wren <= '1';
	 data_ram_input <= x"000000009";
	 data_ram_addr <=  "0000011";    -- 
	 wait for 10 ns;
	 data_ram_wren <= '1';
	 data_ram_input <= x"000000010";
	 data_ram_addr <=  "0000100";    -- 
	 wait for 10 ns; 
	 data_ram_wren <= '0';
	 wait;  
	end process;
	
	
	process (clk)
	begin
	   if rising_edge(clk) then
	       clk_counter <= clk_counter +1;
	   end if;
	end process;
	

END bhv;









